Studying at the University of Verona

Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.

This information is intended exclusively for students already enrolled in this course.
If you are a new student interested in enrolling, you can find information about the course of study on the course page:

Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026

The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.

The Study plan 2008/2009 will be available by May 2nd. While waiting for it to be published, consult the Study plan for the current academic year at the following link.

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TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.




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Teaching code

4S00034

Coordinator

Francesca Monti

Credits

6

Also offered in courses:

Language

Italian

Scientific Disciplinary Sector (SSD)

FIS/01 - EXPERIMENTAL PHYSICS

Period

1st Semester dal Oct 1, 2009 al Jan 31, 2010.

Learning outcomes

Aim of the course is to give knowledge of the physics of semiconductor devices (p-n junction, MOSFET, CMOS; BJT) and related logic gates. The student will be able to compare various logic families in terms of their physical characteristics and performances.

Program

Recall of Classical and Atomic Physics: work and energy, electric field, potential and potential energy, electric current, Ohm's law, linear circuits, resistivity and temperature dependence in metals and semiconductors, Bohr atom, table of elements

Crystal structure and electric conduction in metals and semiconductors: electron gas model of metals, conduction current in metals; covalent bond in semiconductors and the concept of hole, doped semiconductors, band theory, conduction and diffusion current in semiconductors

p-n junction: polarized and non polarized junction, I-V characteristics in direct and reverse polarization for Si and Ge, breakdown, junction diode, Zener diodes, OR/AND gates with diodes, commutation time

FET transistors: enrichment and depletion MOSFET, NMOS and PMOS. MOSFET inverters, CMOS, noise margins and commutation times

BJT transistors and RTL inverter: common emitter configuration, RTL inverter, noise margins, commutation times

Elementary digital circuits: basic gates in MOS and bipolar technologies: NOR and NAND MOS, NOR and NAND CMOS, NAND DTL, NAND HTL, NAND TTL; OR/NOR ECL

Comparison of logic families: propagation delay, power dissipation, noise margins, fan-out

Laboratory activities: logic gates study and characterization by Spice

Examination Methods

Oral

Students with disabilities or specific learning disorders (SLD), who intend to request the adaptation of the exam, must follow the instructions given HERE