Studying at the University of Verona

Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.

This information is intended exclusively for students already enrolled in this course.
If you are a new student interested in enrolling, you can find information about the course of study on the course page:

Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026

The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.

CURRICULUM TIPO:

1° Year 

ModulesCreditsTAFSSD
12
B
ING-INF/05
12
B
ING-INF/05
6
B
ING-INF/05
6
B
ING-INF/05

2° Year   activated in the A.Y. 2015/2016

ModulesCreditsTAFSSD
6
B
INF/01
Altre attivita' formative (taf f)
4
F
-
ModulesCreditsTAFSSD
12
B
ING-INF/05
12
B
ING-INF/05
6
B
ING-INF/05
6
B
ING-INF/05
activated in the A.Y. 2015/2016
ModulesCreditsTAFSSD
6
B
INF/01
Altre attivita' formative (taf f)
4
F
-
Modules Credits TAF SSD
Between the years: 1°- 2°

Legend | Type of training activity (TTA)

TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.




S Placements in companies, public or private institutions and professional associations

Teaching code

4S02911

Coordinator

Franco Fummi

Credits

6

Language

Italian

Scientific Disciplinary Sector (SSD)

ING-INF/05 - INFORMATION PROCESSING SYSTEMS

Period

I sem. dal Oct 1, 2014 al Jan 30, 2015.

Learning outcomes

The aim of this course is the presentation of some design automation techniques for embedded systems covering the entire design flow through modeling, verification, synthesis and testing. The most important design languages are introduced such as the most advanced EDA tools.

Program

Introduction to embedded systems.

Embedded systems modeling.

Embedded systems design alternatives.

System-level design.

Transactional Level Modeling (TLM) by using SystemC.

Introduction to Assertion-based verification (ABV).

Platform-based design.

Embedded software design.

HW/SW/NET co-simulation.

Register transfer level (RTL) hardware description languages (VHDL/SystemC).

Automatic synthesis from RTL designs.

The problem of testing.

The problem of dependability.

Reference texts
Author Title Publishing house Year ISBN Notes
Daniel D. Gajski Embedded system design: modeling, synthesis and verification Springer 2009 978-1-4419-0504-8
William Fornaciari, Carlo Brandolese Sistemi Embedded - sviluppo hardware e software per sistemi dedicati (Edizione 1) Pearson Education Italia 2007 9788871923420

Examination Methods

Written examination and laboratory activity.

Students with disabilities or specific learning disorders (SLD), who intend to request the adaptation of the exam, must follow the instructions given HERE

Teaching materials e documents