Teaching code

4S02717

Credits

12

Coordinatore

Tiziano Villa

Language

Italian

Scientific Disciplinary Sector (SSD)

ING-INF/05 - INFORMATION PROCESSING SYSTEMS

Elearning Seminars

The teaching is organized as follows:

Learning outcomes

Module:
-------

The first part of the class describes how to implement an algorithm into a digital architecture. Some design alternatives are presented ranging from a pure software, running on a general purpose computer, to an ad-hoc hardware implementation. The goal is to understand the compilation steps transforming an high-level programming language into machine-level code.

The second part of the class describes the architecture of an operating system, with the objective to understand the management and synchronization of processes and resources of a general-purpose computing system.

Program

Module:
-------

Fundamentals: information coding, Boolean functions, arithmetic.

Digital design: combinational circuits, sequential circuits, special purpose architectures (control unit + data path), programmable units.

Computer architecture: basic principles, instruction set, processor, memory hierarchy, I/O organization.

Practical exercises: assembly programming of LC-3 architecture.


Evolution and role of the operating system. Architectural concepts. Organization and functionality of an operating system.

Process Management: Processes. Process status. Context switch. Process creation and termination. Thread. User-level threads and kernel-level threads. Process cooperation and communication: shared memory, messages. Direct and indirect communication.

Scheduling: CPU and I/O burst model. Long term, short term and medium term scheduling. Preemption. Scheduling criteria. Scheduling algorithm: FCFS, SJF, priority-based, RR, HRRN, multiple queues with and without feedback. Algorithm evaluation: deterministic and probabilistic models, simulation.

Process synchronization: data coherency, atomic operations. Critical sections. SW approaches for mutual exclusion: Peterson and Dekker's algorithms, baker's algorithm. HW for mutual exclusion: test and set, swap. Synchronization constructs: semaphores, mutex, monitor.

Deadlock: Deadlock conditions. Resource allocation graph. Deadlock prevention. Deadlock avoidance. Banker's algorithm. Deadlock detection e recovery.

Memory management: Main memory. Logical and physical addressing. Relocation, address binding. Swapping. Memory allocation. Internal and external fragmentation. Paging. HW for paging: TLB. Page table. Multi-level paging. Segmentation. Segment table. Segmentation with paging.

Virtual memory: Paging on demand. Page fault management. Page substitution algorithms: FIFO, optimal, LRU, LRU approximations. Page buffering. Frame allocation: local and global allocation. Thrashing. Working set model. Page fault frequency.

Secondary memory. Logical and physical structure of disks. Latency time. Disk scheduling algorithms: FCFS, SSTF, SCAN, C-SCAN, LOOK, C-LOOK. RAID.

File System: file, attributes and related operation. File types. Sequential and direct access. Directory structure. Access permissions and modes. Consistency semantics. File system structure. File system mounting. Allocation techniques: adjacent, linked, indexed. Free space management: bit vector, lists. Directory implementation: linear list, hash table.

I/O subsystem: I/O Hardware. I/O techniques: programmed I/O, interrupt, DMA. Device driver and application interface. I/O kernel services: scheduling, buffering, caching, spooling.

Bibliography

Examination Methods

Module:
-------

Written text for the theoretical part (3/4 of final grade).

Programming projects and written text for the laboratory (1/4 of final grade).