Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Study Plan
This information is intended exclusively for students already enrolled in this course.If you are a new student interested in enrolling, you can find information about the course of study on the course page:
Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.
1° Year
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2° Year activated in the A.Y. 2017/2018
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Modules | Credits | TAF | SSD |
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Modules | Credits | TAF | SSD |
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Modules | Credits | TAF | SSD |
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2 courses to be chosen among the following
Legend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Design automation of embedded systems (2017/2018)
Teaching code
4S02912
Academic staff
Coordinator
Credits
6
Language
Italian
Scientific Disciplinary Sector (SSD)
INF/01 - INFORMATICS
Period
I sem. dal Oct 2, 2017 al Jan 31, 2018.
Learning outcomes
This class introduces the fundamental algorithms for the automatic design of embedded systems, with particular emphasis on data structures to design and optimize digital systems and on automatic techniques for synthesis, verification and testing of embedded systems.
Program
Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.
Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.
Dynamic assertion-based verification. Assertion qualification: assertion coverage, vacuum cleaning. Automatic generation of assertions.
Author | Title | Publishing house | Year | ISBN | Notes |
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Gary D.Hachtel, Fabio Somenzi | Logic Synthesis and Verification Algorithms (Edizione 1) | Kluwer Academic Publishers | 1996 | 0792397460 |
Examination Methods
The exam includes:
- a written test with exercises and open questions covering the three parts of the program
- a project chosen by the student in one of the three parts of the program, under the supervision of the related instructor
The final score is the average of the scores in the written test and in the class project.
Teaching materials e documents
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Calendario delle lezioni (pdf, it, 45 KB, 12/19/17)
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Sintesi Logica - Esercitazioni (pdf, it, 275 KB, 12/1/17)
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Sintesi Logica - Laboratorio CUDD - cudd-2.5.0-bin64.tar.gz (x-gzip, it, 1735 KB, 12/2/17)
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Sintesi Logica - Laboratorio CUDD - cudd-2.5.0-src.tar.gz (x-gzip, it, 1028 KB, 12/2/17)
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Sintesi Logica - Laboratorio CUDD - cudd-tutorial.tar.gz (x-gzip, it, 1 KB, 12/2/17)
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Sintesi Logica - Laboratorio CUDD - Lezione (pdf, it, 426 KB, 12/2/17)
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Sintesi Logica - Laboratorio Espresso (x-gzip, it, 1853 KB, 10/17/17)
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Sintesi Logica - Laboratorio SIS - Lezione (pdf, it, 1478 KB, 12/2/17)
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Sintesi Logica - Laboratorio SIS - sis-1.3.6.bin.amd64.tar.gz (x-gzip, it, 11628 KB, 12/2/17)
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Sintesi Logica - Laboratorio SIS - sis-1.3.6.src.tar.gz (x-gzip, it, 2999 KB, 12/2/17)
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Sintesi Logica - Teoria (x-gzip, en, 1965 KB, 12/1/17)