Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Study Plan
This information is intended exclusively for students already enrolled in this course.If you are a new student interested in enrolling, you can find information about the course of study on the course page:
Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.
1° Year
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2° Year activated in the A.Y. 2019/2020
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2 modules among the followingLegend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Automated System Verification (2018/2019)
Teaching code
4S003252
Teacher
Coordinator
Credits
6
Language
Italian
Scientific Disciplinary Sector (SSD)
INF/01 - INFORMATICS
Period
II semestre dal Mar 4, 2019 al Jun 14, 2019.
Learning outcomes
The course aims to provide the theoretical basis of the main techniques of specification and verification of finite-state systems. In particular, with reference to transition systems, trace-based techniques, linear time logic and branched-time logic.
At the end of the course the student will have to demonstrate that he has acquired the knowledge necessary to formally reason on finite-state systems, with emphasis on the problems of correctness solved automatically (model-checking), through logical operational methods (traces) (temporal logics) and algorithms.
This knowledge will enable the student to: i) specify and formally test properties of correctness of simple systems presented as transition systems; ii) use time logics (linear and branched) for the specification of properties; iii) master semantic methods for temporal logics.
At the end of the course the student will be able to: i) compare temporal logics for the automatic verification and choose from these the most appropriate according to the context of use; when defining a verification process make the most appropriate design choices; ii) continue the studies independently in the context of formal verification.
Program
System Verification:
the model checking approach
Modelling Concurrent Systems:
transition Systems,
parallelism and communication,
state-space xplosion
Linear-Time Properties:
safety and invariants,
liveness,
fairness
Linear Temporal Logic:
syntax,
semantics,
fairness,
model checking
Computation Tree Logic:
syntax,
semantics,
expressiveness of CTL vs. LTL,
fairness,
symbolic model checking,
CTL∗
Equivalences and Abstraction:
bisimulation ,
bisimulation and CTL∗ equivalence
| Author | Title | Publishing house | Year | ISBN | Notes |
|---|---|---|---|---|---|
| Christel Baier and Joost-Pieter Katoen | Principles of Model Checking | MIT press | 2008 |
Examination Methods
Written exam (one and a half hours to perform the task).
In order to pass the exam, the student must have sufficient knowledge of all the topics (including the proofs of the theorems) and the ability to solve exercises similar to those seen during the lessons.
Better is the knowledge of course topics, better is the result of exam.
