Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Study Plan
This information is intended exclusively for students already enrolled in this course.If you are a new student interested in enrolling, you can find information about the course of study on the course page:
Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.
1° Year
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2° Year activated in the A.Y. 2019/2020
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2 modules among the followingLegend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Embedded systems design (2018/2019)
Teaching code
4S02911
Credits
6
Language
Italian
Scientific Disciplinary Sector (SSD)
ING-INF/05 - INFORMATION PROCESSING SYSTEMS
The teaching is organized as follows:
Teoria
Laboratorio
Learning outcomes
The aim of this course is the presentation of some design automation techniques for embedded systems covering the entire design flow through modeling, verification, synthesis and testing. The most important design languages are introduced such as the most advanced EDA tools.
At the end of the course, the students will be able to understand the main components of an embedded system and they will know how to:
- identify the best architecture of an ambedded system starting from specification;
- partition among HW and SW an high-level functionality with emphasis on the interaction with network and operating system;
- model, design and verify a complex digital device;
- develop embedded software interacting with IoT and cloud architectures.
Program
* Introduction to embedded systems.
* Embedded systems modeling.
* Embedded systems design alternatives.
* System-level design.
* Transaction Level Modeling (TLM) and AMS by using SystemC.
* Introduction to Assertion-based verification (ABV).
* Platform-based design.
* Embedded software design.
* HW/SW/NET co-simulation.
* Register transfer level (RTL) hardware description languages (VHDL/SystemC).
* Automatic synthesis from RTL designs.
* The problem of testing.
* The problem of dependability.
Bibliography
| Activity | Author | Title | Publishing house | Year | ISBN | Notes |
|---|---|---|---|---|---|---|
| Teoria | Daniel D. Gajski | Embedded system design: modeling, synthesis and verification | Springer | 2009 | 978-1-4419-0504-8 | |
| Teoria | Soonhoi Ha, Jürgen Teich | Handbook of Hardware/Software Codesign (Edizione 1) | Springer Netherlands | 2017 | ISBN 978-94-017-7266-2 |
Examination Methods
The exam is composed of two parts: theory and laboratory report.
To pass the exam, the students must show:
- they have understood the principles of embedded system architectures;
- they are able to model and simulate a complex embedded system;
- they are able to design, verify and test a complex digital device;
- they are able to develop embedded software interacting with network and operating system;
- they are able to apply the acquired knowledge to solve application scenarios described by means of exercises, questions and projects.
The final exam consists of a written test containing questions and exercises.
A report of all laboratoty classes must be provided to complete the exam.
Teaching materials e documents
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Detailed program
(it, 33 KB, 11/21/18)
