Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Academic calendar
The academic calendar shows the deadlines and scheduled events that are relevant to students, teaching and technical-administrative staff of the University. Public holidays and University closures are also indicated. The academic year normally begins on 1 October each year and ends on 30 September of the following year.
Course calendar
The Academic Calendar sets out the degree programme lecture and exam timetables, as well as the relevant university closure dates..
| Period | From | To |
|---|---|---|
| I semestre | Oct 1, 2020 | Jan 29, 2021 |
| II semestre | Mar 1, 2021 | Jun 11, 2021 |
| Session | From | To |
|---|---|---|
| Sessione invernale d'esame | Feb 1, 2021 | Feb 26, 2021 |
| Sessione estiva d'esame | Jun 14, 2021 | Jul 30, 2021 |
| Sessione autunnale d'esame | Sep 1, 2021 | Sep 30, 2021 |
| Session | From | To |
|---|---|---|
| Sessione Estiva | Jul 15, 2021 | Jul 15, 2021 |
| Sessione Autunnale | Oct 15, 2021 | Oct 15, 2021 |
| Sessione Invernale | Mar 15, 2022 | Mar 15, 2022 |
| Period | From | To |
|---|---|---|
| Festa dell'Immacolata | Dec 8, 2020 | Dec 8, 2020 |
| Vacanze Natalizie | Dec 24, 2020 | Jan 3, 2021 |
| Epifania | Jan 6, 2021 | Jan 6, 2021 |
| Vacanze Pasquali | Apr 2, 2021 | Apr 5, 2021 |
| Santo Patrono | May 21, 2021 | May 21, 2021 |
| Festa della Repubblica | Jun 2, 2021 | Jun 2, 2021 |
Exam calendar
Exam dates and rounds are managed by the relevant Science and Engineering Teaching and Student Services Unit.
To view all the exam sessions available, please use the Exam dashboard on ESSE3.
If you forgot your login details or have problems logging in, please contact the relevant IT HelpDesk, or check the login details recovery web page.
Should you have any doubts or questions, please check the Enrolment FAQs
Academic staff
Study Plan
The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University. Please select your Study Plan based on your enrolment year.
| Modules | Credits | TAF | SSD |
|---|
1° Year
2° Year
| Modules | Credits | TAF | SSD |
|---|
| Modules | Credits | TAF | SSD |
|---|
Legend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Automated System Verification (2020/2021)
Teaching code
4S003252
Teacher
Coordinatore
Credits
6
Scientific Disciplinary Sector (SSD)
INF/01 - INFORMATICS
Language
Italian
Period
I semestre dal Oct 1, 2020 al Jan 29, 2021.
Learning outcomes
The course aims at providing the foundational concepts of verification on both hardware and software systems, for example by using temporal logic and semantic of traces to represent their behavior. At the end of the course the student (1) will have acquired the technical knowledge of model-based verification (model-checking), (2) will be able to use those knowledge to model behavior of specific hardware and software systems and (3) will be able to continue, potentially in an autonomous way, to study and research the field of technologies for formal verification of systems.
Program
System Verification:
the model checking approach
Modelling Concurrent Systems:
transition Systems,
parallelism and communication,
state-space explosion
Linear-Time Properties:
safety and invariants,
liveness,
fairness
Linear Temporal Logic:
syntax,
semantics,
model checking in LTL
Computation Tree Logic:
syntax,
semantics,
expressiveness of CTL vs. LTL,
symbolic model checking,
CTL∗
Equivalences and Abstraction:
bisimulation
bisimulation and equivalence in CTL*
Bibliografia
| Author | Title | Publishing house | Year | ISBN | Notes |
|---|---|---|---|---|---|
| Christel Baier and Joost-Pieter Katoen | Principles of Model Checking | MIT press | 2008 |
Examination Methods
The exam will be in written form, with the possibility, on demand, and under specified conditions, of an oral integration. Student with an evaluation over 24/30 shall be permitted to require an oral integration. With no such request, mark on written exam will be final.
Written exam will be articulated in two parts. In the first part, the students will be required to discuss the topics given in the lecture with a question for each of the major topics: Modeling concurrency, properties of linear time, linear temporal logic, computation tree logic, CTL*, equivalence and abstraction.
The applied part of the written exam, again for a 50% of the total mark, will check the competence of the students about transition systems, temporal logic model checking, bisimulation, abstraction.
The first part of the oral exam will consist in questions regarding the same topics of the the first part of the written exam. Second part of the oral exam, instead, will consist in a single exercise, on request of the instructor.
Evaluation of the written exam will take into account:
- width of the knowledge of transition systems, temporal logic, abstraction models;
- correctness of the exercises
- completeness of the knowledge of the topics
On the other hand, the oral exam will be evaluated based on:
-analytical completeness in answers to questions;
- competence on the specified topics of the programme;
- correctness and width of the answers.
Students have the right to be examined online by request.
Type D and Type F activities
Le attività formative in ambito D o F comprendono gli insegnamenti impartiti presso l'Università di Verona o periodi di stage/tirocinio professionale.
Nella scelta delle attività di tipo D, gli studenti dovranno tener presente che in sede di approvazione si terrà conto della coerenza delle loro scelte con il progetto formativo del loro piano di studio e dell'adeguatezza delle motivazioni eventualmente fornite.
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | Matlab-Simulink programming | D |
Bogdan Mihai Maris
(Coordinatore)
|
| 1° 2° | Programming Challanges | D |
Romeo Rizzi
(Coordinatore)
|
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | Introduction to 3D printing | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Python programming language | D |
Vittoria Cozza
(Coordinatore)
|
| 1° 2° | HW components design on FPGA | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Rapid prototyping on Arduino | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Protection of intangible assets (SW and invention)between industrial law and copyright | D |
Roberto Giacobazzi
(Coordinatore)
|
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | The fashion lab (1 ECTS) | D |
Maria Caterina Baruffi
(Coordinatore)
|
| 1° 2° | The course provides an introduction to blockchain technology. It focuses on the technology behind Bitcoin, Ethereum, Tendermint and Hotmoka. | D |
Nicola Fausto Spoto
(Coordinatore)
|
Career prospects
Module/Programme news
News for students
There you will find information, resources and services useful during your time at the University (Student’s exam record, your study plan on ESSE3, Distance Learning courses, university email account, office forms, administrative procedures, etc.). You can log into MyUnivr with your GIA login details.
Gestione carriere
Graduation
List of theses and work experience proposals
Attendance
As stated in point 25 of the Teaching Regulations for the A.Y. 2021/2022, attendance at the course of study is not mandatory.Please refer to the Crisis Unit's latest updates for the mode of teaching.
Further services
I servizi e le attività di orientamento sono pensati per fornire alle future matricole gli strumenti e le informazioni che consentano loro di compiere una scelta consapevole del corso di studi universitario.