Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Academic calendar
The academic calendar shows the deadlines and scheduled events that are relevant to students, teaching and technical-administrative staff of the University. Public holidays and University closures are also indicated. The academic year normally begins on 1 October each year and ends on 30 September of the following year.
Course calendar
The Academic Calendar sets out the degree programme lecture and exam timetables, as well as the relevant university closure dates..
| Period | From | To |
|---|---|---|
| I semestre | Oct 1, 2020 | Jan 29, 2021 |
| II semestre | Mar 1, 2021 | Jun 11, 2021 |
| Session | From | To |
|---|---|---|
| Sessione invernale d'esame | Feb 1, 2021 | Feb 26, 2021 |
| Sessione estiva d'esame | Jun 14, 2021 | Jul 30, 2021 |
| Sessione autunnale d'esame | Sep 1, 2021 | Sep 30, 2021 |
| Session | From | To |
|---|---|---|
| Sessione Estiva | Jul 15, 2021 | Jul 15, 2021 |
| Sessione Autunnale | Oct 15, 2021 | Oct 15, 2021 |
| Sessione Invernale | Mar 15, 2022 | Mar 15, 2022 |
| Period | From | To |
|---|---|---|
| Festa dell'Immacolata | Dec 8, 2020 | Dec 8, 2020 |
| Vacanze Natalizie | Dec 24, 2020 | Jan 3, 2021 |
| Epifania | Jan 6, 2021 | Jan 6, 2021 |
| Vacanze Pasquali | Apr 2, 2021 | Apr 5, 2021 |
| Santo Patrono | May 21, 2021 | May 21, 2021 |
| Festa della Repubblica | Jun 2, 2021 | Jun 2, 2021 |
Exam calendar
Exam dates and rounds are managed by the relevant Science and Engineering Teaching and Student Services Unit.
To view all the exam sessions available, please use the Exam dashboard on ESSE3.
If you forgot your login details or have problems logging in, please contact the relevant IT HelpDesk, or check the login details recovery web page.
Should you have any doubts or questions, please check the Enrolment FAQs
Academic staff
Study Plan
The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University. Please select your Study Plan based on your enrolment year.
| Modules | Credits | TAF | SSD |
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| Modules | Credits | TAF | SSD |
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1° Year
| Modules | Credits | TAF | SSD |
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2° Year
| Modules | Credits | TAF | SSD |
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| Modules | Credits | TAF | SSD |
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Legend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Embedded & IoT Systems Design (2020/2021)
Teaching code
4S009003
Credits
6
Language
English
Scientific Disciplinary Sector (SSD)
ING-INF/05 - INFORMATION PROCESSING SYSTEMS
The teaching is organized as follows:
Teoria
Laboratorio
Learning outcomes
The course aims at providing the following knowledge: techniques for the automatic design of embedded and industrial IoT systems, starting from their specifications to go through verification, automatic synthesis and testing. Main languages to deal with this kind of project and the most advanced automatic tools for their manipulation. This is in particular applied to the design, verification and test of cyber-physical production systems.
At the end of the course the student will have to demonstrate that he/she has the following skills to apply the acquired knowledge: identify the best architecture for an embedded and industrial IoT system from the specifications; model, design and verify complex analog / digital devices; develop embedded software and interact with IoT and cloud architectures; partition a functionality between hw, sw with attention to the network and operating systems; build project report highlighting the critical aspects resolved; be able to use additional languages for the design of embedded and industrial IoT systems starting from the ones studied in the course.
Program
* Embedded and IoT Systems Modeling:
- Course introduction
- Embedded systems modeling
- SysML for systems modeling
* System Level Description Languages
- SystemC-based design
- SystemC TLM
* Hardware Description Languages:
- HDL introduction
- VHDL syntax
- verilog syntax
- HDL timing simulation
* Register Transfer Level Synthesis:
- RTL synthesis: VHDL
- RTL synthesis: Verilog
* High-Level Synthesis:
- High-level synthesis (HLS) intoduction
- High-level synthesis scheduling
- High-level synthesis allocation
- High-level synthesis application
* Platforms and Virtual Platforms:
- Virtual platform modeling: IP-Xact
- Virtual platform design and FMI
- SystemVerilog introduction
- SystemVerilog main characteristics
- SystemC & Verilog AMS
* Embedded Software:
- Embedded software modeling
- Model-based design of embedded software
- Embedded AI software modeling
* Industry 4.0 – CPPSs:
- Industry 4.0: software hierarchy
- Industry 4.0: digital twin
- IoT and Industrial IoT
- IoT and Cloud
On-line lectures following the official calendar on: https://univr.zoom.us/j/84729760071
Bibliography
| Activity | Author | Title | Publishing house | Year | ISBN | Notes |
|---|---|---|---|---|---|---|
| Teoria | Soonhoi Ha, Jürgen Teich | Handbook of Hardware/Software Codesign (Edizione 1) | Springer Netherlands | 2017 | ISBN 978-94-017-7266-2 |
Examination Methods
The exam is composed of two parts: theory and laboratory report.
To pass the exam, the students must show:
- they have understood the principles of embedded and IoT system architectures;
- they are able to model and simulate a complex embedded and IoT system;
- they are able to design, verify and test a complex digital device;
- they are able to develop embedded software interacting with network and operating system;
- they are able to apply the acquired knowledge to solve application scenarios in the context of Industry 4.0.
The final exam consists of a written test containing questions and exercises.
A report of all laboratoty classes must be provided to complete the exam.
Teaching materials
-
Course presentation
(it, 11937 KB, 30/09/20)
-
Detailed program
(it, 33 KB, 08/01/21)
Type D and Type F activities
Le attività formative in ambito D o F comprendono gli insegnamenti impartiti presso l'Università di Verona o periodi di stage/tirocinio professionale.
Nella scelta delle attività di tipo D, gli studenti dovranno tener presente che in sede di approvazione si terrà conto della coerenza delle loro scelte con il progetto formativo del loro piano di studio e dell'adeguatezza delle motivazioni eventualmente fornite.
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | Matlab-Simulink programming | D |
Bogdan Mihai Maris
(Coordinatore)
|
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | Introduction to 3D printing | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Python programming language | D |
Vittoria Cozza
(Coordinatore)
|
| 1° 2° | HW components design on FPGA | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Rapid prototyping on Arduino | D |
Franco Fummi
(Coordinatore)
|
| 1° 2° | Protection of intangible assets (SW and invention)between industrial law and copyright | D |
Roberto Giacobazzi
(Coordinatore)
|
| years | Modules | TAF | Teacher |
|---|---|---|---|
| 1° 2° | The fashion lab (1 ECTS) | D |
Maria Caterina Baruffi
(Coordinatore)
|
| 1° 2° | The course provides an introduction to blockchain technology. It focuses on the technology behind Bitcoin, Ethereum, Tendermint and Hotmoka. | D |
Nicola Fausto Spoto
(Coordinatore)
|
Career prospects
Module/Programme news
News for students
There you will find information, resources and services useful during your time at the University (Student’s exam record, your study plan on ESSE3, Distance Learning courses, university email account, office forms, administrative procedures, etc.). You can log into MyUnivr with your GIA login details.
Further services
I servizi e le attività di orientamento sono pensati per fornire alle future matricole gli strumenti e le informazioni che consentano loro di compiere una scelta consapevole del corso di studi universitario.
Graduation
List of theses and work experience proposals
| theses proposals | Research area |
|---|---|
| Domain Adaptation | Computer Science and Informatics: Informatics and information systems, computer science, scientific computing, intelligent systems - Computer graphics, computer vision, multi media, computer games |
| Domain Adaptation | Computer Science and Informatics: Informatics and information systems, computer science, scientific computing, intelligent systems - Machine learning, statistical data processing and applications using signal processing (e.g. speech, image, video) |
| Domain Adaptation | Computing Methodologies - IMAGE PROCESSING AND COMPUTER VISION |
| Domain Adaptation | Computing methodologies - Machine learning |
Attendance
As stated in point 25 of the Teaching Regulations for the A.Y. 2021/2022, attendance at the course of study is not mandatory.Please refer to the Crisis Unit's latest updates for the mode of teaching.
