Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Study Plan
This information is intended exclusively for future freshmen who will enroll for the 2025/2026 academic year.If you are already enrolled in this course of study, consult the information available on the course page:
Laurea magistrale in Computer Engineering for Intelligent Systems [LM-32] - Enrollment until 2024/2025The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.
1° Year
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2° Year It will be activated in the A.Y. 2026/2027
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4 modules among:
- 1st year - Embedded operating systems, Embedded & IoT Systems design, Robotics, Computer vision, Advanced visual computing and 3D modeling - delivered in 2025/2026
- 2nd year - Advanced control systems - delivered in 2026/20273 modules among:
- 2nd year - Advanced methods for biomedical signal processing, Neurohealth, Medical robotics, Internet of Medical things - delivered in 2026/2027
- 1st or 2nd year - Mathematical modeling for Industrial and medical digital twins, Cloud computing and distributed systems - delivered in 2025/2026 or in 2026/2027 Legend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Systems verification & testing (2025/2026)
Teaching code
4S009017
Academic staff
Coordinator
Credits
6
Also offered in courses:
- Systems verification & testing of the course Master's Degree in in Computer Engineering for Intelligent Systems
Language
English
Scientific Disciplinary Sector (SSD)
ING-INF/05 - INFORMATION PROCESSING SYSTEMS
Period
1st semester dal Oct 1, 2025 al Jan 30, 2026.
Courses Single
Authorized
Learning objectives
The course aims to train students in the field of languages and automatic tools that underpin the verification and testing methodologies of complex digital and analog systems. In particular, the main objective of the course is to explain how it is possible to represent complex systems through virtual platforms in relation to their physical realization and to guarantee the functional safety and certification process of the devices that compose them. Upon completion of the course, the students must demonstrate that they have acquired the fundamental knowledge to understand the methodologies and tools necessary to verify and test complex analog / digital devices, to guarantee their functional safety, and to certify them. This knowledge will allow the students to: represent analog / digital systems in the form of virtual platforms; define verification methods based on dynamic and semi-formal techniques; develop approaches for testing and fault tolerance; use, integrate, and develop automatic tools for the modelling, verification and testing of analog / digital systems; activate certification processes.
Prerequisites and basic notions
To best learn the topics covered in the course, it is necessary to have knowledge in the field of HW/SW system design.
Program
A. Systems modeling and veriifcation
- SystemVerilog
- ABV introduction
- ABV - specification languages
- ABV - assertion automatic generation
- ABV - assertion qualification: coverage
- ABV - assertion qualification: vacuity
- ABV - assertion qualification: overspecification
B. Systems testing and certiifcation
- Faults-defects-errors definition
- Digital faults modeling
- Analog faults modeling
- verilog-AMS
- Systemc-AMS
- Gate-level simulation
- Fault simulation
- Combinational ATPG
- Sequantial ATPG
- Design for testability
- Self-testing circuits
- Fault tollerance
- Functional safety
- Certification for safety
Bibliography
Didactic methods
The course is organized in lectures, exercises and practical computer activities.
Learning assessment procedures
The final exam consists of two parts:
- a written exam lasting a maximum of two hours, containing four questions consisting of open-ended questions and exercises (two related to the verification area and two related to the testing area);
- a report describing the application of everything learned in the laboratory exercises to a case study. Alternatively, students may complete a project related to their thesis.
The exam is the same for both attending and non-attending students. There are no midterm tests.
Evaluation criteria
To pass the exam, students must demonstrate that they:
- understand the principles related to the verification and testing of a system;
- are able to present their arguments in a precise and organic way without digressions;
- know how to apply the knowledge acquired to solve application problems presented in the form of exercises, questions and projects.
Criteria for the composition of the final grade
The final grade is given by the weighted sum of the theory grade and the laboratory report.
Exam language
English
