Studying at the University of Verona

Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.

Study Plan

A.A. 2024/2025 A.A. 2023/2024 A.A. 2022/2023 A.A. 2021/2022 A.A. 2020/2021 A.A. 2019/2020 A.A. 2018/2019 A.A. 2017/2018 A.A. 2016/2017 A.A. 2015/2016 A.A. 2014/2015 A.A. 2013/2014 A.A. 2012/2013 A.A. 2011/2012 A.A. 2010/2011 A.A. 2009/2010

This information is intended exclusively for students already enrolled in this course.
If you are a new student interested in enrolling, you can find information about the course of study on the course page:

Master's degree in Computer Science and Engineering - Enrollment from 2025/2026

The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.

The Study plan 2008/2009 will be available by May 2nd. While waiting for it to be published, consult the Study plan for the current academic year at the following link.

Legend | Type of training activity (TTA)

TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.

A Basic activities
B Characterizing activities
C Related or complementary activities
D Activities to be chosen by the student
E Final examination
F Other training activities
S Placements in companies, public or private institutions and professional associations

Design automation of embedded systems   (2009/2010)

Teaching code

4S02912

Academic staff

Tiziano Villa, Franco Fummi, Graziano Pravadelli

Coordinator

Tiziano Villa

Credits

6

Also offered in courses:

Language

Italian

Scientific Disciplinary Sector (SSD)

INF/01 - INFORMATICS

Period

1st Semester dal Oct 1, 2009 al Jan 31, 2010.

Seminars 0

Learning outcomes

The course introduces the fundamental methodologies for the automatic design of embedded systems, with particular emphasis on algorithms for synthesis, verification and testing.

Program

Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.

Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.

Assertion coverage, vacuum cleaning, automatic generation of checkers.

Examination Methods

Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.

Students with disabilities or specific learning disorders (SLD), who intend to request the adaptation of the exam, must follow the instructions given HERE

Teaching materials e documents