Automated System Verification
Scientific Disciplinary Sector (SSD)
INF/01 - INFORMATICS
II semestre dal Mar 4, 2019 al Jun 14, 2019.
The course aims to provide the theoretical basis of the main techniques of specification and verification of finite-state systems. In particular, with reference to transition systems, trace-based techniques, linear time logic and branched-time logic.
At the end of the course the student will have to demonstrate that he has acquired the knowledge necessary to formally reason on finite-state systems, with emphasis on the problems of correctness solved automatically (model-checking), through logical operational methods (traces) (temporal logics) and algorithms.
This knowledge will enable the student to: i) specify and formally test properties of correctness of simple systems presented as transition systems; ii) use time logics (linear and branched) for the specification of properties; iii) master semantic methods for temporal logics.
At the end of the course the student will be able to: i) compare temporal logics for the automatic verification and choose from these the most appropriate according to the context of use; when defining a verification process make the most appropriate design choices; ii) continue the studies independently in the context of formal verification.
the model checking approach
Modelling Concurrent Systems:
parallelism and communication,
safety and invariants,
Linear Temporal Logic:
Computation Tree Logic:
expressiveness of CTL vs. LTL,
symbolic model checking,
Equivalences and Abstraction:
bisimulation and CTL∗ equivalence
|Christel Baier and Joost-Pieter Katoen
||Principles of Model Checking
Written exam (one and a half hours to perform the task).
In order to pass the exam, the student must have sufficient knowledge of all the topics (including the proofs of the theorems) and the ability to solve exercises similar to those seen during the lessons.
Better is the knowledge of course topics, better is the result of exam.