Studying at the University of Verona

Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.

Type D and Type F activities

Le attività formative in ambito D o F comprendono gli insegnamenti impartiti presso l'Università di Verona o periodi di stage/tirocinio professionale.
Nella scelta delle attività di tipo D, gli studenti dovranno tener presente che in sede di approvazione si terrà conto della coerenza delle loro scelte con il progetto formativo del loro piano di studio e dell'adeguatezza delle motivazioni eventualmente fornite.

 

I semestre From 10/1/20 To 1/29/21
years Modules TAF Teacher
Matlab-Simulink programming D Bogdan Mihai Maris (Coordinator)
II semestre From 3/1/21 To 6/11/21
years Modules TAF Teacher
Introduction to 3D printing D Franco Fummi (Coordinator)
Python programming language D Vittoria Cozza (Coordinator)
HW components design on FPGA D Franco Fummi (Coordinator)
Rapid prototyping on Arduino D Franco Fummi (Coordinator)
Protection of intangible assets (SW and invention)between industrial law and copyright D Roberto Giacobazzi (Coordinator)
List of courses with unassigned period
years Modules TAF Teacher
Subject requirements: mathematics D Rossana Capuani
The fashion lab (1 ECTS) D Maria Caterina Baruffi (Coordinator)
LaTeX Language D Enrico Gregorio (Coordinator)

Teaching code

4S010210

Coordinator

Franco Fummi

Credits

3

Also offered in courses:

Language

Italian

Scientific Disciplinary Sector (SSD)

NN - -

Period

II semestre dal Mar 1, 2021 al Jun 11, 2021.

Learning outcomes

Introduction to basic concepts of electronics.
Introduction to cross-compilation.
Design and development of simple electrical circuits. Introduction to edge-computing and cloud-based data delivery.

Program

- 1 lesson (2 hours): Introduction on the electronic fundamentals, development environment setup and creation of a first circuit;

- 2 lesson (2 hours): Prototype design (circuit design and component selection) and user interaction.

- 3 lesson (2 hours): Design of circuits for sensing and actuation, and introduction to network communications.

- 4 lesson (2 hours): Edge-computing and sending data to the cloud.

Examination Methods

The exam will consist of a project of your choice. This project may be chosen from a set of proposed projects or proposed by the student (after validation from the professor).

For the exam organization, please, contact:
- Enrico Fraccaroli <enrico.fraccaroli@univr.it>
- Nicola Dall'Ora <nicola.dallora@univr.it>

Students with disabilities or specific learning disorders (SLD), who intend to request the adaptation of the exam, must follow the instructions given HERE