Teaching code

4S008224

Credits

6

Coordinator

Davide Quaglia

Language

Italian

Scientific Disciplinary Sector (SSD)

ING-INF/05 - INFORMATION PROCESSING SYSTEMS

Courses Single

Authorized

Moodle Seminars 0

The teaching is organized as follows:

Learning objectives

The aim of the course is to provide the theory and practice to implement an algorithm in hardware, exploring a spectrum of options ranging from dedicated specialized devices to programs on a gene-ral-purpose processor. The students will understand how a processor works and how a high-level program is translated into machine language and then executed. At the end of the course, the students will be able to design specialized hardware for simple algo-rithms; translate simple programs from an high-level specification to machine language

Prerequisites and basic notions

None

Program

Introduction to computer architecture. Realization of elementary logic functions with switch circuits and CMOS logic gates.
Types of circuits: digital and analog; combinatorial and sequential; synchronous and asynchronous.
Introduction to combinatorial logic.
Axioms and theorems of Boolean algebra.
Rewriting expressions with the rules of Boolean algebra.
Normal conjunctive and disjunctive forms.
Incompletely specified functions.
Boolean hypercubes and Karnaugh maps.
Logical minimization using Karnaugh maps.
Implicants, first and essential.
Calculation of prime implicants of functions with one or more outputs.
Exact minimization with the Quine-McCluskey method.
Delays in combinational circuits and oscillatory circuits.
Smooth and programmable logic for combinational circuits. Selectors and deselectors.
Design of combinational circuits from specification in natural language to implementation in a given technology.
Electronic systems description languages.
Binary arithmetic with negative numbers.
Overflow conditions in two's complement.
Representation of real numbers with fixed-point and floating-point arithmetic.
Carry propagation, carry advance, carry selection adders. Binary adder modulus and sign and number adder in BCD coding.
Binary subtractor.
Arithmetic-logical unit.
Introduction to multi-level logic.
Conversion between AND/OR, OR/AND and NAND, NOR.
Introduction to sequential circuits.
Latch
Static memory cell with a ring pair of inverters.
SR memory cell with a pair of crossed NOR (or NAND) gates.
Flip-flop
Synchronous timing methodologies.
Basic registers. Shift registers. Counters.
Analysis of shift registers and counters from the logic diagram to the state graph.
Synthesis of shift registers and counters from state graph to logic diagram.
Analysis and synthesis of finite state machines.
Synchronized Moore, Mealy, Mealy machines.
Transformation from Moore machines to timed Moore machines.
Comparison between timed Moore machines and synchronized Mealy machines.
Minimization of the states of finite state machines.
Impact of state minimization on logical minimization.
State coding of finite state machines.
Sequential circuit design from specification to finite state machine, to minimized logic representation.
Relationships between critical paths and frequency/period of a sequential circuit.
Architecture of a processor.
Control unit and executive unit.
Fetch-decode-execute cycle of an instruction.
Types of instructions. Fundamental registers.
Interaction with the input-output units.
Execution cycles of register addition operations, reading/writing from/to memory, jumping (synchronous Mealy machine).
Extended finite state machines.
Design of dedicated processors: example of the processor that implements the Euclid algorithm of the Greatest Common Divisor.
Introduction to the LC-3 architecture.

Bibliography

Didactic methods

Classroom and laboratory lessons.

Learning assessment procedures

Written test for the theoretical part with questions and exercises (5/6 of the final grade).
Written test or programming project in the assembly language of the LC3 architecture for the laboratory (1/6 of final grade).

Evaluation criteria

Understanding of the basics of computer architecture. from Boolean algebra to finite state machines, to the design of combinational and sequential logic.

Understanding of the machine language LC-3 and solution of simple programming assignments.

Criteria for the composition of the final grade

Written test for the theoretical part with questions and exercises (5/6 of the final grade).
Written test or programming project in the assembly language of the LC3 architecture for the laboratory (1/6 of final grade).

Exam language

Italiano