CAD Group: ITC'99 Benchmarks (2nd release)

Overview

The ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino (I99T) are a set of circuits whose characteristics are typical of synthesized circuits. For each bench both the RT-level VHDL description and the synthesized Gate-Level netlist are available. In April 2002 new RT-Level VHDL benchmarks were added to the set and more gate-level circuits were synthesized.
I99T benchmarks are available from http://www.cad.polito.it/tools/itc99.html, while further benchmarks and tools developed by the CAD Group are available here.

You can find a detailed descriptions of benchmarks and an experimental RT-level ATPG tool in the article "RT-Level ITC 99 Benchmarks and First ATPG Results", IEEE Design & Test of Computers, July-August 2000. We also maintain an updated list of references to research results obtained on these benchmarks.

Benchmarks main characteristics are sketched below:

Fully synthesizable RT-Level VHDL descriptions (in Synopsys Design Compiler description styles).
No compiler specific directive.
Require only IEEE standard logic and arithmetic packages.
Completely synchronous circuits.
One single-phase clock signal connected directly to memory elements.
Global reset signal always available.
No internal memories (except register banks).
No 3-state busses.
No or wired connections.

VHDL RT-Level descriptions range from a small, monolithic circuit (1 entity, 1 process, 70 lines) to a large, multi-entity, multi-process one (11 entities, 33 processes, 1,424 lines). At the Gate-Level, netlists range from an s27-sized circuit (2 inputs, 29 gates, 4 flip-flops, 150 faults) to a circuit more than 3 times larger that the largest ISCAS'89 (37 inputs, 69,917 gates, 3,320 flip-flops, 429,712 faults).

VHDL descriptions were synthesized to netlists using both standard (std) options and optimized (opt) options. The former may contains completely useless gates with no inputs and no outputs. Optimized gate-level circuits superseded "stripped" (e.g., b04s) gate-level circuits.

NAME VHDL TYPE GATE LEVEL FAULT
LINE PROC GATE PI PO FF L0 L1 COMP COLL

b01 110 1 std 49 2 2 5 0 0 260 114

opt 49 2 2 5 0 0 260 118

b02 70 1 std 28 1 1 4 0 0 148 62

opt 27 1 1 4 0 0 144 60

b03 141 1 std 160 4 4 30 0 0 872 386

opt 153 4 4 30 0 0 844 386

b04 102 1 std 737 8 11 66 8 4 4,102 1,646

opt 628 11 8 66 0 0 3,532 1,502

b05 332 3 std^* 998 1 36 34 8 33 5,732 2,440

opt 574 1 36 34 0 0 3,214 1,522

b06 128 1 std 56 2 6 9 0 0 276 134

opt 55 2 6 9 0 0 272 134

b07 92 1 std 441 1 8 49 0 0 2,460 1,072

opt 427 1 8 49 0 0 2,446 1,111

b08 89 1 std 183 9 4 21 0 0 994 442

opt 171 9 4 21 0 0 932 407

b09 103 1 std 170 1 1 28 0 0 946 403

opt 160 1 1 28 0 0 902 410

b10 167 1 std 206 11 6 17 0 0 1,118 485

opt 180 11 6 17 0 0 1,010 454

b11 118 1 std 770 7 6 31 6 5 4,332 1,726

opt 548 7 6 31 0 0 3,276 1,422

b12 569 4 std 1,076 5 6 121 0 0 6,306 2,856

opt 1,006 5 6 121 0 0 5,994 2,805

b13 296 5 std 362 10 10 53 2 1 1,906 830

opt 317 10 10 53 0 0 1,694 779

b14 509 1 std 10,098 32 54 245 18 6 58,348 22,634

opt 5,678 32 54 245 0 0 35,264 15,999

b14_1 509 1 std 6,900 32 54 245 13 6 39,890 15,492

opt 4,379 32 54 245 0 0 27,040 12,307

b15 671 3 std 8,922 36 70 449 21 9 53,018 21,776

opt 7,577 36 70 449 0 0 47,414 21,072

b15_1 671 3 std 13,098 36 70 449 169 14 75,618 28,787

opt 7,974 36 70 448 0 0 50,384 21,852

b17 810 15 std 32,326 37 97 1,415 243 37 190,784 76,485

opt 24,305 37 97 1,414 0 0 154,220 68,037

b17_1 810 15 std 39,665 37 97 1,415 511 47 230,360 87,958

opt 24,571 37 97 1,412 0 0 156,256 67,693

b18 1,424 33 std^** 114,621 36 23 3,320 1,072 110 667,008 263,967

opt 73,243 36 23 3,270 0 0 463,570 206,736

b18_1 1,424 33 std^** 108,482 36 23 3,320 1,061 109 630,894 250,717

opt 71,611 36 23 3,270 0 0 453,088 202,812

b19 1,491 10 std^** 231,320 21 30 6,642 2,153 217 1,345,442 533,142

b19_1 1,491 10 std^** 219,424 21 30 6,642 2,132 218 1,275,720 507,476

b20 1,085 3 std 20,226 32 22 490 43 14 117,750 45,395

opt 12,501 32 22 490 0 0 78,788 35,667

b20_1 1,085 3 std 14,443 32 22 490 33 14 83,906 33,191

opt 10,709 32 22 490 0 0 67,158 30,749

b21 1,089 3 std 20,571 32 22 490 43 15 120,000 46,090

opt 12,678 32 22 490 0 0 79,556 35,994

b21_1 1,089 3 std 14,442 32 22 490 33 15 84,084 32,884

opt 10,206 32 22 490 0 0 63,732 29,091

b22 1,613 4 std 29,951 32 22 735 63 11 174,786 67,472

opt 18,086 32 22 703 0 0 113,308 51,277

b22_1 1,613 4 std 21,772 32 22 735 50 14 126,670 49,881

opt 15,713 32 22 703 0 0 98,006 44,771

CAPTION

LINES: VHDL lines
PROC: Number of process
TYPE: Synthesis type (standard or optimized)
GATES: Number of gates
PI: Number of primary inputs
PO: Number of primary outputs
FF: Number of flip-flops
L0/1: Number of logic-zero/logic-one
COMP: Number of faults in complete fault list
COLL: Number of faults in collapsed (reduced) fault list

NOTES

*) More than one connections between the same pair of gates
**) Dandling gates

NAME	ORIGINAL FUNCTIONALITY
b01	FSM that compares serial flows
b02	FSM that recognizes BCD numbers
b03	Resource arbiter
b04	Compute min and max
b05	Elaborate the contents of a memory
b06	Interrupt handler
b07	Count points on a straight line
b08	Find inclusions in sequences of numbers
b09	Serial to serial converter
b10	Voting system
b11	Scramble string with variable cipher
b12	1-player game (guess a sequence)
b13	Interface to meteo sensors
b14	Viper processor (subset)
b15	80386 processor (subset)
b16	Hard to initialize circuit (parametric)
b17	Three copies of b15
b18	Two copies of b14 and two of b17
b19	Two copies of b14 and two of b17
b20	A copy of b14 and a modified version of b14
b21	Two copies of b14
b22	A copy of b14 and two modified versions of b14

itc99-poli2.tar.gz	Complete tarball including VHDL descriptions, EDIF netlists and fault lists (126,851,723 bytes)
itc99-poli2-vhd.tar.gz	RT-Level VHDL descriptions (65,085 bytes)
itc99-poli2-edf.tar.gz	Synthesized netlists in edf (EDIF) format (48,998,976 bytes)
itc99-poli2-fau.tar.gz	Gate-level fault lists (51,906,297 bytes)
itc99-poli2-bench.tar.gz	Synthesized netlists in bench (ISCAS'89) format (18,987,069 bytes)¹
itc99-poli2-blif.tar.gz	Synthesized netlists in blif format (6,828,380 bytes)
itc99-poli2-breset.tar.gz	Some netlists in bench format with explicit resets (2,446,431 bytes)²
¹ due to format restrictions, not all circuits are available in bench format.
² netlists modified by Marong Phadoongsidhi, the perl script is included in the tarball.

itc99-poli.tar.gz	Complete tarball (10,110,139 bytes)
itc99-poli-vhd.tar.gz	RT-Level VHDL descriptions (25,019 bytes)
itc99-poli-edf.tar.gz	Synthesized netlists in flattened EDIF format (6,126,783 bytes)
itc99-poli-bench.tar.gz	Synthesized netlists in bench (ISCAS'89) format (573,709 bytes)^*
itc99-poli-fau.tar.gz	Gate-level fault lists (3,359,547 bytes)
^* due to format restrictions, not all circuits are available in bench format.

Overview

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NAME	VHDL		TYPE	GATE LEVEL						FAULT
NAME	LINE	PROC	TYPE	GATE	PI	PO	FF	L0	L1	COMP	COLL
b01	110	1	std	49	2	2	5	0	0	260	114
b01	110	1	opt	49	2	2	5	0	0	260	118
b02	70	1	std	28	1	1	4	0	0	148	62
b02	70	1	opt	27	1	1	4	0	0	144	60
b03	141	1	std	160	4	4	30	0	0	872	386
b03	141	1	opt	153	4	4	30	0	0	844	386
b04	102	1	std	737	8	11	66	8	4	4,102	1,646
b04	102	1	opt	628	11	8	66	0	0	3,532	1,502
b05	332	3	std^*	998	1	36	34	8	33	5,732	2,440
b05	332	3	opt	574	1	36	34	0	0	3,214	1,522
b06	128	1	std	56	2	6	9	0	0	276	134
b06	128	1	opt	55	2	6	9	0	0	272	134
b07	92	1	std	441	1	8	49	0	0	2,460	1,072
b07	92	1	opt	427	1	8	49	0	0	2,446	1,111
b08	89	1	std	183	9	4	21	0	0	994	442
b08	89	1	opt	171	9	4	21	0	0	932	407
b09	103	1	std	170	1	1	28	0	0	946	403
b09	103	1	opt	160	1	1	28	0	0	902	410
b10	167	1	std	206	11	6	17	0	0	1,118	485
b10	167	1	opt	180	11	6	17	0	0	1,010	454
b11	118	1	std	770	7	6	31	6	5	4,332	1,726
b11	118	1	opt	548	7	6	31	0	0	3,276	1,422
b12	569	4	std	1,076	5	6	121	0	0	6,306	2,856
b12	569	4	opt	1,006	5	6	121	0	0	5,994	2,805
b13	296	5	std	362	10	10	53	2	1	1,906	830
b13	296	5	opt	317	10	10	53	0	0	1,694	779
b14	509	1	std	10,098	32	54	245	18	6	58,348	22,634
b14	509	1	opt	5,678	32	54	245	0	0	35,264	15,999
b14_1	509	1	std	6,900	32	54	245	13	6	39,890	15,492
b14_1	509	1	opt	4,379	32	54	245	0	0	27,040	12,307
b15	671	3	std	8,922	36	70	449	21	9	53,018	21,776
b15	671	3	opt	7,577	36	70	449	0	0	47,414	21,072
b15_1	671	3	std	13,098	36	70	449	169	14	75,618	28,787
b15_1	671	3	opt	7,974	36	70	448	0	0	50,384	21,852
b17	810	15	std	32,326	37	97	1,415	243	37	190,784	76,485
b17	810	15	opt	24,305	37	97	1,414	0	0	154,220	68,037
b17_1	810	15	std	39,665	37	97	1,415	511	47	230,360	87,958
b17_1	810	15	opt	24,571	37	97	1,412	0	0	156,256	67,693
b18	1,424	33	std^**	114,621	36	23	3,320	1,072	110	667,008	263,967
b18	1,424	33	opt	73,243	36	23	3,270	0	0	463,570	206,736
b18_1	1,424	33	std^**	108,482	36	23	3,320	1,061	109	630,894	250,717
b18_1	1,424	33	opt	71,611	36	23	3,270	0	0	453,088	202,812
b19	1,491	10	std^**	231,320	21	30	6,642	2,153	217	1,345,442	533,142
b19_1	1,491	10	std^**	219,424	21	30	6,642	2,132	218	1,275,720	507,476
b20	1,085	3	std	20,226	32	22	490	43	14	117,750	45,395
b20	1,085	3	opt	12,501	32	22	490	0	0	78,788	35,667
b20_1	1,085	3	std	14,443	32	22	490	33	14	83,906	33,191
b20_1	1,085	3	opt	10,709	32	22	490	0	0	67,158	30,749
b21	1,089	3	std	20,571	32	22	490	43	15	120,000	46,090
b21	1,089	3	opt	12,678	32	22	490	0	0	79,556	35,994
b21_1	1,089	3	std	14,442	32	22	490	33	15	84,084	32,884
b21_1	1,089	3	opt	10,206	32	22	490	0	0	63,732	29,091
b22	1,613	4	std	29,951	32	22	735	63	11	174,786	67,472
b22	1,613	4	opt	18,086	32	22	703	0	0	113,308	51,277
b22_1	1,613	4	std	21,772	32	22	735	50	14	126,670	49,881
b22_1	1,613	4	opt	15,713	32	22	703	0	0	98,006	44,771

CAPTION
LINES: VHDL lines PROC: Number of process TYPE: Synthesis type (standard or optimized) GATES: Number of gates PI: Number of primary inputs	PO: Number of primary outputs FF: Number of flip-flops L0/1: Number of logic-zero/logic-one COMP: Number of faults in complete fault list COLL: Number of faults in collapsed (reduced) fault list
NOTES
) More than one connections between the same pair of gates *) Dandling gates