Studying at the University of Verona

Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.

This information is intended exclusively for students already enrolled in this course.
If you are a new student interested in enrolling, you can find information about the course of study on the course page:

Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026

The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.

CURRICULUM TIPO:

1° Year 

ModulesCreditsTAFSSD
12
B
ING-INF/05
6
B
ING-INF/05
6
B
ING-INF/05
12
B
ING-INF/05

2° Year   activated in the A.Y. 2013/2014

ModulesCreditsTAFSSD
6
B
INF/01
Altre attivita' formative
4
F
-
ModulesCreditsTAFSSD
12
B
ING-INF/05
6
B
ING-INF/05
6
B
ING-INF/05
12
B
ING-INF/05
activated in the A.Y. 2013/2014
ModulesCreditsTAFSSD
6
B
INF/01
Altre attivita' formative
4
F
-
Modules Credits TAF SSD
Between the years: 1°- 2°

Legend | Type of training activity (TTA)

TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.




S Placements in companies, public or private institutions and professional associations

Teaching code

4S02910

Coordinator

Nicola Bombieri

Credits

6

Language

Italian

Scientific Disciplinary Sector (SSD)

ING-INF/05 - INFORMATION PROCESSING SYSTEMS

Period

II semestre dal Mar 4, 2013 al Jun 14, 2013.

Learning outcomes

The course will provide theoretical and practical knowledge on definition, design and analysis of advanced computer architecture with more emphasis on multicore and GP-GPU architectures.

Program

Module THEORY (32h):
-) Introduction to parallelism and parallel architectures.
-) Parallel architecture models and programming.
-) Performance evaluation and analysis
-) Amdhal’s law and metrics for performance measurement.
-) Pipeline basics and advanced concepts.
-) Instruction-level parallelism (ILP).
-) Advanced branch prediction, static scheduling e speculation.
-) Memory hierarchy: basics and advanced concepts.
-) Virtual memory.
-) Thread-level parallelism (TLP).
-) Cache coherence in shared memory architectures.
-) Snoopy protocols.
-) Data-level parallelism (DLP).
-) General purpose Graphic Processing Unit (GP-GPU).
-) GP-GPU programming: CUDA and OpenCL.
-) Introduction to Grid and Cloud Computing.

Module LAB (24h):
-) Parallel compilers for multicore architectures (OpenMP).
-) Parallel compilers for clusters (MPI).
-) GP-GPU programming: CUDA, OpenCL.

To attend the teaching successfully, it is recommended that the student has already acquired skills in:
*) Basics of computer architectures. In particular: the instruction set, processing unit, memory hierarchy, pipeline.
*) Basics of operating systems. In particular: the concept of process and thread, memory virtualization.
*) Basics of Programming. In particular: basic concepts of C programming and Assembly

Reference texts
Author Title Publishing house Year ISBN Notes
John L. Hennessy and David A. Patterson Computer Architecture - A Quantitative Approach (Edizione 4) Morgan Kaufmann 2007

Examination Methods

Preliminary test + lab project

Students with disabilities or specific learning disorders (SLD), who intend to request the adaptation of the exam, must follow the instructions given HERE