Studying at the University of Verona
Here you can find information on the organisational aspects of the Programme, lecture timetables, learning activities and useful contact details for your time at the University, from enrolment to graduation.
Study Plan
This information is intended exclusively for students already enrolled in this course.If you are a new student interested in enrolling, you can find information about the course of study on the course page:
Laurea magistrale in Ingegneria e scienze informatiche - Enrollment from 2025/2026The Study Plan includes all modules, teaching and learning activities that each student will need to undertake during their time at the University.
Please select your Study Plan based on your enrollment year.
1° Year
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2° Year activated in the A.Y. 2012/2013
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Tre insegnamenti a scelta tra i seguenti
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Tre insegnamenti a scelta tra i seguenti
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Legend | Type of training activity (TTA)
TAF (Type of Educational Activity) All courses and activities are classified into different types of educational activities, indicated by a letter.
Design automation of embedded systems (2012/2013)
Teaching code
4S02912
Academic staff
Coordinator
Credits
6
Language
Italian
Scientific Disciplinary Sector (SSD)
INF/01 - INFORMATICS
Period
I semestre dal Oct 1, 2012 al Jan 31, 2013.
Learning outcomes
The course introduces the fundamental algorithms for the automatic design of embedded systems, with particular emphasis on data structures to design and optimize digital systems and on automatic techniques for synthesis, verification and testing of embedded systems.
Program
Representation of logic functions, multi-valued logic, binary decision diagrams, multi-level logic, netlist optimization with respect to area, timing and power consumption. State machines and sequential circuits, micro-architectural optimization.
Definition, characterization and simulation of defects, fault and error modeling, fault and error simulation. Test generation for combinatorial and sequential circuits, built-in self test, fault tolerance.
Dynamic assertion-based verification. Assertion qualification: assertion coverage, vacuum cleaning.
Examination Methods
Written examination (ON/OFF) plus a project chosen in one of the three main areas covered in the class.
Teaching materials e documents
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Calendario del corso (pdf, it, 45 KB, 11/28/12)
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Presentazione del corso (pdf, it, 839 KB, 10/1/12)
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Sintesi Logica - Esercitazioni (pdf, it, 187 KB, 10/2/12)
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Sintesi Logica - Laboratorio CUDD (pdf, en, 426 KB, 11/12/12)
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Sintesi Logica - Laboratorio CUDD - esercizio DDcal (x-gzip, en, 1 KB, 11/12/12)
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Sintesi Logica - Laboratorio Espresso (pdf, en, 638 KB, 10/1/12)
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Sintesi Logica - Laboratorio espresso - espresso-64.bin.tar.gz (x-gzip, en, 102 KB, 10/1/12)
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Sintesi Logica - Laboratorio espresso - espresso.lesson-examples.tar.gz (x-gzip, en, 1 KB, 10/1/12)
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Sintesi Logica - Laboratorio espresso - espresso.src.tar.gz (x-gzip, en, 176 KB, 10/1/12)
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Sintesi Logica - Laboratorio - guida installazione (pdf, it, 819 KB, 10/22/12)
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Sintesi Logica - Laboratorio SIS (pdf, en, 814 KB, 10/1/12)
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Sintesi Logica - Laboratorio SIS - sis-1.3.6.bin.amd64.tar.gz (x-gzip, it, 11628 KB, 10/1/12)
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Sintesi Logica - Laboratorio SIS - sis-1.3.6.src.tar.gz (x-gzip, it, 2999 KB, 10/1/12)
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Sintesi Logica - Laboratorio - siti pacchetti (x-gzip, it, 0 KB, 10/1/12)
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Sintesi Logica - Teoria (x-gzip, en, 1733 KB, 10/2/12)
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Verifica - Lezioni Pravadelli (zip, it, 6030 KB, 12/4/12)